NIIN Output Data
NIIN:
NSN:
Item Name:
MICROCIRCUIT , DIGITAL
Definition:
A MICROCIRCUIT SPECIFICALLY DESIGNED TO GENERATE, MODIFY, OR PROCESS ELECTRICAL SIGNALS WHICH OPERATE WITH TWO DISTINCT OR BINARY STATES. THESE STATES ARE COMMONLY REFERRED TO AS ON AND OFF, TRUE AND FALSE, HIGH AND LOW, OR "1" AND "0".
Reference/Part Number
| Part Number | CAGE | Status | RNCC | RNVC | DAC | RNAAC | MSDS | SADC |
|---|---|---|---|---|---|---|---|---|
| SN5420-5 | 01295 | A | 3 | 2 | 5 | TA | ||
| 507862-1 | 96214 | A | 1 | 2 | 2 | TA |
CAGE Information
| Code | Company |
|---|---|
| 01295 | TEXAS INSTRUMENTS INCORPORATED DBA T |
| 96214 | RAYTHEON COMPANY |
Characteristics (Decoded)
| MRC | Requirements Statement | Clear Text Reply |
|---|---|---|
| FEAT | SPECIAL FEATURES | FORMED LEADS |
| FEAT | SPECIAL FEATURES | FORMED LEADS |
| AFGA | OPERATING TEMP RANGE | -55.0/+125.0 DEG CELSIUS |
| PRMT | PRECIOUS MATERIAL | GOLD |
| AEHX | MAXIMUM POWER DISSIPATION RATING | 20.0 MILLIWATTS |
| CWSG | TERMINAL SURFACE TREATMENT | GOLD |
| CQSZ | INCLOSURE CONFIGURATION | FLAT PACK |
| TTQY | TERMINAL TYPE AND QUANTITY | 14 FLAT LEADS |
| PMLC | PRECIOUS MATERIAL AND LOCATION | TERMINALS GOLD |
| AFJQ | STORAGE TEMP RANGE | -65.0/+150.0 DEG CELSIUS |
| ADAT | BODY WIDTH | 0.200 INCHES MINIMUM AND 0.300 INCHES MAXIMUM |
| CZEN | VOLTAGE RATING AND TYPE PER CHARACTERISTIC | 5.5 VOLTS MAXIMUM POWER SOURCE |
| CSSL | DESIGN FUNCTION AND QUANTITY | 2 GATE, NAND |
| TEST | TEST DATA DOCUMENT | 96214-507862 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING) |
| CQZP | INPUT CIRCUIT PATTERN | DUAL 4 INPUT |
| ADAU | BODY HEIGHT | 0.008 INCHES MINIMUM AND 0.100 INCHES MAXIMUM |
| CBBL | FEATURES PROVIDED | POSITIVE OUTPUTS AND HERMETICALLY SEALED AND MONOLITHIC AND MEDIUM SPEED AND W/TOTEM POLE OUTPUT |
| CQSJ | INCLOSURE MATERIAL | CERAMIC AND GLASS |
| CQWX | OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| CZEQ | TIME RATING PER CHACTERISTIC | 29.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 15.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |
| CTFT | CASE OUTLINE SOURCE AND DESIGNATOR | -0-004-AE JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| ADAQ | BODY LENGTH | 0.220 INCHES MINIMUM AND 0.250 INCHES MAXIMUM |