NIIN Output Data
NIIN:
NSN:
Item Name:
MICROCIRCUIT , DIGITAL
Definition:
A MICROCIRCUIT SPECIFICALLY DESIGNED TO GENERATE, MODIFY, OR PROCESS ELECTRICAL SIGNALS WHICH OPERATE WITH TWO DISTINCT OR BINARY STATES. THESE STATES ARE COMMONLY REFERRED TO AS ON AND OFF, TRUE AND FALSE, HIGH AND LOW, OR "1" AND "0".
Reference/Part Number
| Part Number | CAGE | Status | RNCC | RNVC | DAC | RNAAC | MSDS | SADC |
|---|---|---|---|---|---|---|---|---|
| SN54110J | 01295 | A | 5 | 2 | 3 | TX | ||
| SN54110J-00 | 01295 | A | 3 | 2 | 3 | TX |
CAGE Information
| Code | Company |
|---|---|
| 01295 | TEXAS INSTRUMENTS INCORPORATED DBA T |
Federal Supply Class
Title
MICROCIRCUITS, ELECTRONIC
Inclusions:
INCLUDES INTEGRATED CIRCUIT DEVICES; INTEGRATED CIRCUIT MODULES, INTEGRATED ELECTRONIC DEVICES: HYBRID, MAGNETIC, MOLECULAR, OPTO-ELECTRONIC, AND THIN FILM.
Exclusions:
EXCLUDES SINGLE CIRCUIT ELEMENTS SUCH AS CAPACITORS; RESISTORS; DIODES AND TRANSISTORS; PRINTED CIRCUIT BOARDS AND CIRCUIT CARD ASSEMBLIES; AND FILTERS AND NETWORKS.
Characteristics (Decoded)
| MRC | Requirements Statement | Clear Text Reply |
|---|---|---|
| CQSZ | INCLOSURE CONFIGURATION | DUAL-IN-LINE |
| CQSZ | INCLOSURE CONFIGURATION | DUAL-IN-LINE |
| AFGA | OPERATING TEMP RANGE | -55.0/+125.0 DEG CELSIUS |
| CTFT | CASE OUTLINE SOURCE AND DESIGNATOR | T0-116 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| CQZP | INPUT CIRCUIT PATTERN | 9 INPUT |
| CSSL | DESIGN FUNCTION AND QUANTITY | 1 FLIP-FLOP, J-K, AND INPUT MASTER SLAVE AND 1 FLIP-FLOP, J-K, CLOCKED |
| AEHX | MAXIMUM POWER DISSIPATION RATING | 100.0 MILLIWATTS |
| CBBL | FEATURES PROVIDED | EDGE TRIGGERED AND POSITIVE OUTPUTS AND MONOLITHIC AND HERMETICALLY SEALED AND W/CLEAR |
| ADAU | BODY HEIGHT | 0.140 INCHES MINIMUM AND 0.180 INCHES MAXIMUM |
| FEAT | SPECIAL FEATURES | WITH DATA LOCKOUT |
| AFJQ | STORAGE TEMP RANGE | -65.0/+150.0 DEG CELSIUS |
| ADAT | BODY WIDTH | 0.220 INCHES MINIMUM AND 0.280 INCHES MAXIMUM |
| CQSJ | INCLOSURE MATERIAL | CERAMIC AND GLASS |
| CQWX | OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| CZEQ | TIME RATING PER CHACTERISTIC | 30.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 25.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |
| ADAQ | BODY LENGTH | 0.660 INCHES MINIMUM AND 0.785 INCHES MAXIMUM |