National Stock Number (NSN) Output Data
NSN:
NIIN:
Item Name:
MICROCIRCUIT , DIGITAL
Definition:
A MICROCIRCUIT SPECIFICALLY DESIGNED TO GENERATE, MODIFY, OR PROCESS ELECTRICAL SIGNALS WHICH OPERATE WITH TWO DISTINCT OR BINARY STATES. THESE STATES ARE COMMONLY REFERRED TO AS ON AND OFF, TRUE AND FALSE, HIGH AND LOW, OR "1" AND "0".
Reference/Part Number
| Part Number | CAGE | Status | RNCC | RNVC | DAC | RNAAC | MSDS | SADC |
|---|---|---|---|---|---|---|---|---|
| SC5231004 | 96682 | A | 3 | 2 | 1 | KE | ||
| 5410DM | 07263 | A | 5 | 1 | 6 | TX |
CAGE Information
| Code | Company |
|---|---|
| 07263 | FAIRCHILD SEMICONDUCTOR CORP |
| 96682 | GENISCO TECHNOLOGY CORPORATION |
Federal Supply Class
Title
MICROCIRCUITS, ELECTRONIC
Inclusions:
INCLUDES INTEGRATED CIRCUIT DEVICES; INTEGRATED CIRCUIT MODULES, INTEGRATED ELECTRONIC DEVICES: HYBRID, MAGNETIC, MOLECULAR, OPTO-ELECTRONIC, AND THIN FILM.
Exclusions:
EXCLUDES SINGLE CIRCUIT ELEMENTS SUCH AS CAPACITORS; RESISTORS; DIODES AND TRANSISTORS; PRINTED CIRCUIT BOARDS AND CIRCUIT CARD ASSEMBLIES; AND FILTERS AND NETWORKS.
Characteristics (Decoded)
| MRC | Requirements Statement | Clear Text Reply |
|---|---|---|
| CQSZ | INCLOSURE CONFIGURATION | DUAL-IN-LINE |
| CQSZ | INCLOSURE CONFIGURATION | DUAL-IN-LINE |
| AFGA | OPERATING TEMP RANGE | -55.0/+125.0 DEG CELSIUS |
| ADAT | BODY WIDTH | 0.245 INCHES MINIMUM AND 0.271 INCHES MAXIMUM |
| ABKW | OVERALL HEIGHT | 0.365 INCHES MAXIMUM |
| CBBL | FEATURES PROVIDED | MONOLITHIC AND HERMETICALLY SEALED AND W/RESISTOR |
| TTQY | TERMINAL TYPE AND QUANTITY | 14 PRINTED CIRCUIT |
| ADAU | BODY HEIGHT | 0.185 INCHES NOMINAL |
| ADAQ | BODY LENGTH | 0.750 INCHES MINIMUM AND 0.785 INCHES MAXIMUM |
| AFJQ | STORAGE TEMP RANGE | -65.0/+150.0 DEG CELSIUS |
| CQZP | INPUT CIRCUIT PATTERN | TRIPLE 3 INPUT |
| CZEN | VOLTAGE RATING AND TYPE PER CHARACTERISTIC | 5.5 VOLTS MAXIMUM POWER SOURCE |
| CQSJ | INCLOSURE MATERIAL | CERAMIC |
| CSSL | DESIGN FUNCTION AND QUANTITY | 3 GATE, NAND |
| CQWX | OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| CZEQ | TIME RATING PER CHACTERISTIC | 22.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 15.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |
| CWSG | TERMINAL SURFACE TREATMENT | SOLDER |