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National Stock Number (NSN) Output Data

NSN:
NIIN:
Item Name:
MICROCIRCUIT , DIGITAL

Definition:

A MICROCIRCUIT SPECIFICALLY DESIGNED TO GENERATE, MODIFY, OR PROCESS ELECTRICAL SIGNALS WHICH OPERATE WITH TWO DISTINCT OR BINARY STATES. THESE STATES ARE COMMONLY REFERRED TO AS ON AND OFF, TRUE AND FALSE, HIGH AND LOW, OR "1" AND "0".

Reference/Part Number

Part Number CAGE Status RNCC RNVC DAC RNAAC MSDS SADC
SN5440F 01295 A 3 2 3 TX

CAGE Information

Code Company
01295 TEXAS INSTRUMENTS INCORPORATED DBA T

Federal Supply Class

Title

MICROCIRCUITS, ELECTRONIC

Inclusions:

INCLUDES INTEGRATED CIRCUIT DEVICES; INTEGRATED CIRCUIT MODULES, INTEGRATED ELECTRONIC DEVICES: HYBRID, MAGNETIC, MOLECULAR, OPTO-ELECTRONIC, AND THIN FILM.

Exclusions:

EXCLUDES SINGLE CIRCUIT ELEMENTS SUCH AS CAPACITORS; RESISTORS; DIODES AND TRANSISTORS; PRINTED CIRCUIT BOARDS AND CIRCUIT CARD ASSEMBLIES; AND FILTERS AND NETWORKS.

Characteristics (Decoded)

MRC Requirements Statement Clear Text Reply
AFGA OPERATING TEMP RANGE -55.0/+125.0 DEG CELSIUS
AFGA OPERATING TEMP RANGE -55.0/+125.0 DEG CELSIUS
AEHX MAXIMUM POWER DISSIPATION RATING 52.0 MILLIWATTS
ADAU BODY HEIGHT 0.035 INCHES MINIMUM AND 0.050 INCHES MAXIMUM
ADAQ BODY LENGTH 0.250 INCHES MINIMUM AND 0.260 INCHES MAXIMUM
CQSJ INCLOSURE MATERIAL GLASS AND METAL
CWSG TERMINAL SURFACE TREATMENT GOLD
CZEN VOLTAGE RATING AND TYPE PER CHARACTERISTIC -1.5 VOLTS MINIMUM POWER SOURCE AND 5.5 VOLTS MAXIMUM POWER SOURCE
CQSZ INCLOSURE CONFIGURATION FLAT PACK
TTQY TERMINAL TYPE AND QUANTITY 14 FLAT LEADS
AFJQ STORAGE TEMP RANGE -65.0/+150.0 DEG CELSIUS
CBBL FEATURES PROVIDED POSITIVE OUTPUTS AND HERMETICALLY SEALED AND MONOLITHIC AND W/TOTEM POLE OUTPUT
CQZP INPUT CIRCUIT PATTERN DUAL 4 INPUT
CZEQ TIME RATING PER CHACTERISTIC 22.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT
CQWX OUTPUT LOGIC FORM TRANSISTOR-TRANSISTOR LOGIC
PMLC PRECIOUS MATERIAL AND LOCATION TERMINALS GOLD AND BODY GOLD
ADAT BODY WIDTH 0.140 INCHES MINIMUM AND 0.150 INCHES MAXIMUM
CSSL DESIGN FUNCTION AND QUANTITY 2 GATE, NAND BUFFER
CTFT CASE OUTLINE SOURCE AND DESIGNATOR T0-84 JOINT ELECTRON DEVICE ENGINEERING COUNCIL

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