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National Stock Number (NSN) Output Data

NSN:
NIIN:
Item Name:
MICROCIRCUIT , DIGITAL

Definition:

A MICROCIRCUIT SPECIFICALLY DESIGNED TO GENERATE, MODIFY, OR PROCESS ELECTRICAL SIGNALS WHICH OPERATE WITH TWO DISTINCT OR BINARY STATES. THESE STATES ARE COMMONLY REFERRED TO AS ON AND OFF, TRUE AND FALSE, HIGH AND LOW, OR "1" AND "0".

Reference/Part Number

Part Number CAGE Status RNCC RNVC DAC RNAAC MSDS SADC
10030174-102 94580 A 3 2 1 TX
SN54H73J00 01295 A 5 1 6 TX

CAGE Information

Code Company
01295 TEXAS INSTRUMENTS INCORPORATED DBA T
94580 HONEYWELL INTERNATIONAL INC DBA HONE

Federal Supply Class

Title

MICROCIRCUITS, ELECTRONIC

Inclusions:

INCLUDES INTEGRATED CIRCUIT DEVICES; INTEGRATED CIRCUIT MODULES, INTEGRATED ELECTRONIC DEVICES: HYBRID, MAGNETIC, MOLECULAR, OPTO-ELECTRONIC, AND THIN FILM.

Exclusions:

EXCLUDES SINGLE CIRCUIT ELEMENTS SUCH AS CAPACITORS; RESISTORS; DIODES AND TRANSISTORS; PRINTED CIRCUIT BOARDS AND CIRCUIT CARD ASSEMBLIES; AND FILTERS AND NETWORKS.

Characteristics (Decoded)

MRC Requirements Statement Clear Text Reply
CQSZ INCLOSURE CONFIGURATION DUAL-IN-LINE
CQSZ INCLOSURE CONFIGURATION DUAL-IN-LINE
AFGA OPERATING TEMP RANGE -55.0/+125.0 DEG CELSIUS
CRHL BIT QUANTITY (NON-CORE) 5
CBBL FEATURES PROVIDED MONOLITHIC AND HIGH SPEED AND POSITIVE OUTPUTS AND W/CLEAR AND HERMETICALLY SEALED AND W/ENABLE
CTFT CASE OUTLINE SOURCE AND DESIGNATOR T0-116 JOINT ELECTRON DEVICE ENGINEERING COUNCIL
CZEQ TIME RATING PER CHACTERISTIC 21.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 27.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT
CSSL DESIGN FUNCTION AND QUANTITY 2 FLIP-FLOP, J-K, MASTER SLAVE AND 2 FLIP-FLOP, J-K, CLOCKED AND 2 FLIP-FLOP, PULSE TRIGGERED
TTQY TERMINAL TYPE AND QUANTITY 14 PRINTED CIRCUIT
ADAU BODY HEIGHT 0.140 INCHES MINIMUM AND 0.180 INCHES MAXIMUM
AFJQ STORAGE TEMP RANGE -65.0/+150.0 DEG CELSIUS
AEHX MAXIMUM POWER DISSIPATION RATING 200.0 MILLIWATTS
ADAT BODY WIDTH 0.220 INCHES MINIMUM AND 0.280 INCHES MAXIMUM
CQZP INPUT CIRCUIT PATTERN DUAL 4 INPUT
TEST TEST DATA DOCUMENT 94580-10030174 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING)
CQSJ INCLOSURE MATERIAL CERAMIC AND GLASS
CQWX OUTPUT LOGIC FORM TRANSISTOR-TRANSISTOR LOGIC
CWSG TERMINAL SURFACE TREATMENT SOLDER
ADAQ BODY LENGTH 0.660 INCHES MINIMUM AND 0.785 INCHES MAXIMUM

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SN54H73J00 , SN54H73J00 , 5962-00-163-4120 , 5962001634120 , 001634120 , 10030174-102 , SN54H73J00 ,