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Part Number

Part Number:
NSN:
NIIN:
Item Name:
MICROCIRCUIT , DIGITAL

Definition:

A MICROCIRCUIT SPECIFICALLY DESIGNED TO GENERATE, MODIFY, OR PROCESS ELECTRICAL SIGNALS WHICH OPERATE WITH TWO DISTINCT OR BINARY STATES. THESE STATES ARE COMMONLY REFERRED TO AS ON AND OFF, TRUE AND FALSE, HIGH AND LOW, OR "1" AND "0".

CAGE Information

Code Company
04713 FREESCALE SEMICONDUCTOR INC.

Federal Supply Class

Title

MICROCIRCUITS, ELECTRONIC

Inclusions:

INCLUDES INTEGRATED CIRCUIT DEVICES; INTEGRATED CIRCUIT MODULES, INTEGRATED ELECTRONIC DEVICES: HYBRID, MAGNETIC, MOLECULAR, OPTO-ELECTRONIC, AND THIN FILM.

Exclusions:

EXCLUDES SINGLE CIRCUIT ELEMENTS SUCH AS CAPACITORS; RESISTORS; DIODES AND TRANSISTORS; PRINTED CIRCUIT BOARDS AND CIRCUIT CARD ASSEMBLIES; AND FILTERS AND NETWORKS.

Characteristics (Decoded)

MRC Requirements Statement Clear Text Reply
CQWX OUTPUT LOGIC FORM DIODE-TRANSISTOR LOGIC
TTQY TERMINAL TYPE AND QUANTITY 10 PIN
AFGA OPERATING TEMP RANGE +0.0/+70.0 DEG CELSIUS
AEHX MAXIMUM POWER DISSIPATION RATING 12.0 MILLIWATTS
CZEN VOLTAGE RATING AND TYPE PER CHARACTERISTIC -1.5 VOLTS MINIMUM POWER SOURCE AND 5.5 VOLTS MAXIMUM POWER SOURCE
AFJQ STORAGE TEMP RANGE -65.0/+150.0 DEG CELSIUS
ADAU BODY HEIGHT 0.165 INCHES MINIMUM AND 0.185 INCHES MAXIMUM
CBBL FEATURES PROVIDED MONOLITHIC AND POSITIVE OUTPUTS AND HERMETICALLY SEALED AND INTERNALLY COMPENSATED
CQSJ INCLOSURE MATERIAL CERAMIC AND GLASS
CZEQ TIME RATING PER CHACTERISTIC 30.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 30.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT
CTFT CASE OUTLINE SOURCE AND DESIGNATOR T0-100 JOINT ELECTRON DEVICE ENGINEERING COUNCIL
ADAR BODY OUTSIDE DIAMETER 0.335 INCHES MINIMUM AND 0.370 INCHES MAXIMUM
TEST TEST DATA DOCUMENT 03538-7836559 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING)
CQSZ INCLOSURE CONFIGURATION CAN
CSSL DESIGN FUNCTION AND QUANTITY 2 GATE, NAND-NOR
CWSG TERMINAL SURFACE TREATMENT SOLDER
CQZP INPUT CIRCUIT PATTERN DUAL 2 INPUT

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