Part Number
Part Number:
NSN:
NIIN:
Item Name:
MICROCIRCUIT , DIGITAL
Definition:
A MICROCIRCUIT SPECIFICALLY DESIGNED TO GENERATE, MODIFY, OR PROCESS ELECTRICAL SIGNALS WHICH OPERATE WITH TWO DISTINCT OR BINARY STATES. THESE STATES ARE COMMONLY REFERRED TO AS ON AND OFF, TRUE AND FALSE, HIGH AND LOW, OR "1" AND "0".
CAGE Information
Code | Company |
---|---|
80249 | BAE SYSTEMS INFORMATION AND ELECTRON |
Federal Supply Class
Title
MICROCIRCUITS, ELECTRONIC
Inclusions:
INCLUDES INTEGRATED CIRCUIT DEVICES; INTEGRATED CIRCUIT MODULES, INTEGRATED ELECTRONIC DEVICES: HYBRID, MAGNETIC, MOLECULAR, OPTO-ELECTRONIC, AND THIN FILM.
Exclusions:
EXCLUDES SINGLE CIRCUIT ELEMENTS SUCH AS CAPACITORS; RESISTORS; DIODES AND TRANSISTORS; PRINTED CIRCUIT BOARDS AND CIRCUIT CARD ASSEMBLIES; AND FILTERS AND NETWORKS.
Characteristics (Decoded)
MRC | Requirements Statement | Clear Text Reply |
---|---|---|
AFGA | OPERATING TEMP RANGE | -55.0/+125.0 DEG CELSIUS |
AFGA | OPERATING TEMP RANGE | -55.0/+125.0 DEG CELSIUS |
PRMT | PRECIOUS MATERIAL | GOLD |
CBBL | FEATURES PROVIDED | HERMETICALLY SEALED AND MEDIUM SPEED AND MEDIUM POWER AND EDGE TRIGGERED AND MONOLITHIC AND POSITIVE OUTPUTS AND W/CLEAR |
AEHX | MAXIMUM POWER DISSIPATION RATING | 220.0 MILLIWATTS |
ADAU | BODY HEIGHT | 0.035 INCHES MINIMUM AND 0.050 INCHES MAXIMUM |
ADAQ | BODY LENGTH | 0.250 INCHES MINIMUM AND 0.260 INCHES MAXIMUM |
CQSJ | INCLOSURE MATERIAL | GLASS AND METAL |
CQSZ | INCLOSURE CONFIGURATION | FLAT PACK |
FEAT | SPECIAL FEATURES | FORMED LEADS; INSULATOR FURNISHED |
TTQY | TERMINAL TYPE AND QUANTITY | 14 FLAT LEADS |
AFJQ | STORAGE TEMP RANGE | -65.0/+150.0 DEG CELSIUS |
CZEN | VOLTAGE RATING AND TYPE PER CHARACTERISTIC | 5.5 VOLTS MAXIMUM POWER SOURCE |
PMLC | PRECIOUS MATERIAL AND LOCATION | TERMINAL AND BODY SURFACES GOLD |
CQZP | INPUT CIRCUIT PATTERN | DUAL 4 INPUT |
CQWX | OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
ADAT | BODY WIDTH | 0.140 INCHES MINIMUM AND 0.150 INCHES MAXIMUM |
CZEQ | TIME RATING PER CHACTERISTIC | 39.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 50.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |
CSSL | DESIGN FUNCTION AND QUANTITY | 2 FLIP-FLOP, J-K, CLOCKED AND 2 FLIP-FLOP, J-K, MASTER SLAVE |
CTFT | CASE OUTLINE SOURCE AND DESIGNATOR | T0-84 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |