Part Number
Part Number:
NSN:
NIIN:
Item Name:
MICROCIRCUIT , DIGITAL
Definition:
A MICROCIRCUIT SPECIFICALLY DESIGNED TO GENERATE, MODIFY, OR PROCESS ELECTRICAL SIGNALS WHICH OPERATE WITH TWO DISTINCT OR BINARY STATES. THESE STATES ARE COMMONLY REFERRED TO AS ON AND OFF, TRUE AND FALSE, HIGH AND LOW, OR "1" AND "0".
CAGE Information
| Code | Company |
|---|---|
| 27014 | NATIONAL SEMICONDUCTOR CORPORATION |
Federal Supply Class
Title
MICROCIRCUITS, ELECTRONIC
Inclusions:
INCLUDES INTEGRATED CIRCUIT DEVICES; INTEGRATED CIRCUIT MODULES, INTEGRATED ELECTRONIC DEVICES: HYBRID, MAGNETIC, MOLECULAR, OPTO-ELECTRONIC, AND THIN FILM.
Exclusions:
EXCLUDES SINGLE CIRCUIT ELEMENTS SUCH AS CAPACITORS; RESISTORS; DIODES AND TRANSISTORS; PRINTED CIRCUIT BOARDS AND CIRCUIT CARD ASSEMBLIES; AND FILTERS AND NETWORKS.
Characteristics (Decoded)
| MRC | Requirements Statement | Clear Text Reply |
|---|---|---|
| TEST | TEST DATA DOCUMENT | 96214-538869 SPECIFICATION (INCLUDES ENGINEERING TYPE BULLETINS, BROCHURES,ETC., THAT REFLECT SPECIFICATION TYPE DATA IN SPECIFICATION FORMAT; EXCLUDES COMMERCIAL CATALOGS, INDUSTRY DIRECTORIES, AND SIMILAR TRADE PUBLICATIONS, REFLECTING GENERAL TYPE DATA ON CERTAIN ENVIRONMENTAL AND PERFORMANCE REQUIREMENTS AND TEST CONDITIONS THAT ARE SHOWN AS "TYPICAL |
| CBBL | FEATURES PROVIDED | MONOLITHIC AND W/ENABLE AND PRESETTABLE AND HERMETICALLY SEALED AND POSITIVE OUTPUTS AND W/CLEAR |
| CQSZ | INCLOSURE CONFIGURATION | DUAL-IN-LINE |
| AFGA | OPERATING TEMP RANGE | -55.0/+125.0 DEG CELSIUS |
| CTFT | CASE OUTLINE SOURCE AND DESIGNATOR | T0-116 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| CSSL | DESIGN FUNCTION AND QUANTITY | 2 FLIP-FLOP, J-K, MASTER SLAVE |
| TTQY | TERMINAL TYPE AND QUANTITY | 14 PRINTED CIRCUIT |
| ADAU | BODY HEIGHT | 0.140 INCHES MINIMUM AND 0.180 INCHES MAXIMUM |
| AFJQ | STORAGE TEMP RANGE | -65.0/+150.0 DEG CELSIUS |
| CZEN | VOLTAGE RATING AND TYPE PER CHARACTERISTIC | 5.5 VOLTS MAXIMUM POWER SOURCE |
| ADAT | BODY WIDTH | 0.220 INCHES MINIMUM AND 0.280 INCHES MAXIMUM |
| CQZP | INPUT CIRCUIT PATTERN | DUAL 4 INPUT |
| AEHX | MAXIMUM POWER DISSIPATION RATING | 46.0 MILLIWATTS |
| CQSJ | INCLOSURE MATERIAL | CERAMIC AND GLASS |
| CQWX | OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| CZEQ | TIME RATING PER CHACTERISTIC | 16.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 16.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |
| CWSG | TERMINAL SURFACE TREATMENT | SOLDER |
| ADAQ | BODY LENGTH | 0.660 INCHES MINIMUM AND 0.785 INCHES MAXIMUM |