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Part Number

Part Number:
NSN:
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Item Name:
MICROCIRCUIT , DIGITAL

Definition:

A MICROCIRCUIT SPECIFICALLY DESIGNED TO GENERATE, MODIFY, OR PROCESS ELECTRICAL SIGNALS WHICH OPERATE WITH TWO DISTINCT OR BINARY STATES. THESE STATES ARE COMMONLY REFERRED TO AS ON AND OFF, TRUE AND FALSE, HIGH AND LOW, OR "1" AND "0".

CAGE Information

Code Company
27014 NATIONAL SEMICONDUCTOR CORPORATION

Federal Supply Class

Title

MICROCIRCUITS, ELECTRONIC

Inclusions:

INCLUDES INTEGRATED CIRCUIT DEVICES; INTEGRATED CIRCUIT MODULES, INTEGRATED ELECTRONIC DEVICES: HYBRID, MAGNETIC, MOLECULAR, OPTO-ELECTRONIC, AND THIN FILM.

Exclusions:

EXCLUDES SINGLE CIRCUIT ELEMENTS SUCH AS CAPACITORS; RESISTORS; DIODES AND TRANSISTORS; PRINTED CIRCUIT BOARDS AND CIRCUIT CARD ASSEMBLIES; AND FILTERS AND NETWORKS.

Characteristics (Decoded)

MRC Requirements Statement Clear Text Reply
AFGA OPERATING TEMP RANGE -55.0/+125.0 DEG CELSIUS
CQSJ INCLOSURE MATERIAL GLASS AND METAL
ADAT BODY WIDTH 0.120 INCHES MINIMUM AND 0.150 INCHES MAXIMUM
CZEN VOLTAGE RATING AND TYPE PER CHARACTERISTIC -1.5 VOLTS MINIMUM POWER SOURCE AND 5.5 VOLTS MAXIMUM POWER SOURCE
CQSZ INCLOSURE CONFIGURATION FLAT PACK
TTQY TERMINAL TYPE AND QUANTITY 14 FLAT LEADS
AFJQ STORAGE TEMP RANGE -65.0/+150.0 DEG CELSIUS
CSSL DESIGN FUNCTION AND QUANTITY 1 SHIFT REGISTER, PARALLEL ACCESS
ADAU BODY HEIGHT 0.030 INCHES MINIMUM AND 0.070 INCHES MAXIMUM
CRHL BIT QUANTITY (NON-CORE) 4
AEHX MAXIMUM POWER DISSIPATION RATING 19.0 MILLIWATTS
TEST TEST DATA DOCUMENT 13499-351-7390 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING)
ADAQ BODY LENGTH 0.240 INCHES MINIMUM AND 0.260 INCHES MAXIMUM
CQWX OUTPUT LOGIC FORM TRANSISTOR-TRANSISTOR LOGIC
CQZP INPUT CIRCUIT PATTERN 8 INPUT
CZEQ TIME RATING PER CHACTERISTIC 200.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 200.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT
CBBL FEATURES PROVIDED W/ENABLE AND HERMETICALLY SEALED AND MONOLITHIC AND POSITIVE OUTPUTS
CWSG TERMINAL SURFACE TREATMENT SOLDER
CTFT CASE OUTLINE SOURCE AND DESIGNATOR T0-84 JOINT ELECTRON DEVICE ENGINEERING COUNCIL

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