Part Number
Part Number:
NSN:
NIIN:
Item Name:
MICROCIRCUIT , DIGITAL
Definition:
A MICROCIRCUIT SPECIFICALLY DESIGNED TO GENERATE, MODIFY, OR PROCESS ELECTRICAL SIGNALS WHICH OPERATE WITH TWO DISTINCT OR BINARY STATES. THESE STATES ARE COMMONLY REFERRED TO AS ON AND OFF, TRUE AND FALSE, HIGH AND LOW, OR "1" AND "0".
CAGE Information
Code | Company |
---|---|
07263 | FAIRCHILD SEMICONDUCTOR CORP |
Federal Supply Class
Title
MICROCIRCUITS, ELECTRONIC
Inclusions:
INCLUDES INTEGRATED CIRCUIT DEVICES; INTEGRATED CIRCUIT MODULES, INTEGRATED ELECTRONIC DEVICES: HYBRID, MAGNETIC, MOLECULAR, OPTO-ELECTRONIC, AND THIN FILM.
Exclusions:
EXCLUDES SINGLE CIRCUIT ELEMENTS SUCH AS CAPACITORS; RESISTORS; DIODES AND TRANSISTORS; PRINTED CIRCUIT BOARDS AND CIRCUIT CARD ASSEMBLIES; AND FILTERS AND NETWORKS.
Characteristics (Decoded)
MRC | Requirements Statement | Clear Text Reply |
---|---|---|
AFGA | OPERATING TEMP RANGE | -55.0/+125.0 DEG CELSIUS |
CBBL | FEATURES PROVIDED | HERMETICALLY SEALED AND DARLINGTON-CONNECTED AND SYNCHRONOUS AND ASYNCHRONOUS AND EDGE TRIGGERED AND W/CLEAR AND HIGH SPEED AND W/ENABLE AND MONOLITHIC AND POSITIVE OUTPUTS AND W/STORAGE |
PRMT | PRECIOUS MATERIAL | GOLD |
ADAQ | BODY LENGTH | 0.450 INCHES MAXIMUM |
CQSZ | INCLOSURE CONFIGURATION | FLAT PACK |
PMLC | PRECIOUS MATERIAL AND LOCATION | TERMINALS GOLD |
AFJQ | STORAGE TEMP RANGE | -65.0/+150.0 DEG CELSIUS |
CZEQ | TIME RATING PER CHACTERISTIC | 40.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 55.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |
ADAT | BODY WIDTH | 0.200 INCHES MINIMUM AND 0.300 INCHES MAXIMUM |
CZEN | VOLTAGE RATING AND TYPE PER CHARACTERISTIC | 5.5 VOLTS MAXIMUM POWER SOURCE |
AEHX | MAXIMUM POWER DISSIPATION RATING | 240.0 MILLIWATTS |
ADAU | BODY HEIGHT | 0.008 INCHES MINIMUM AND 0.100 INCHES MAXIMUM |
CQSJ | INCLOSURE MATERIAL | CERAMIC AND GLASS |
CQWX | OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
AGAV | END ITEM IDENTIFICATION | NAVIGATIONAL SET,LORAN,TYPE AN/ARN-101 |
TTQY | TERMINAL TYPE AND QUANTITY | 16 FLAT LEADS |
TEST | TEST DATA DOCUMENT | 35351-154868 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING) |
CQZP | INPUT CIRCUIT PATTERN | 10 INPUT |
CSSL | DESIGN FUNCTION AND QUANTITY | 2 FLIP-FLOP, J-K, CLOCKED AND 2 FLIP-FLOP, J-K, MASTER SLAVE |
CWSG | TERMINAL SURFACE TREATMENT | SOLDER |
CTFT | CASE OUTLINE SOURCE AND DESIGNATOR | -0-004-AH JOINT ELECTRON DEVICE ENGINEERING COUNCIL |