Part Number
Part Number:
NSN:
NIIN:
Item Name:
MICROCIRCUIT , DIGITAL
Definition:
A MICROCIRCUIT SPECIFICALLY DESIGNED TO GENERATE, MODIFY, OR PROCESS ELECTRICAL SIGNALS WHICH OPERATE WITH TWO DISTINCT OR BINARY STATES. THESE STATES ARE COMMONLY REFERRED TO AS ON AND OFF, TRUE AND FALSE, HIGH AND LOW, OR "1" AND "0".
CAGE Information
| Code | Company |
|---|---|
| 18324 | PHILIPS SEMICONDUCTORS INC |
Federal Supply Class
Title
MICROCIRCUITS, ELECTRONIC
Inclusions:
INCLUDES INTEGRATED CIRCUIT DEVICES; INTEGRATED CIRCUIT MODULES, INTEGRATED ELECTRONIC DEVICES: HYBRID, MAGNETIC, MOLECULAR, OPTO-ELECTRONIC, AND THIN FILM.
Exclusions:
EXCLUDES SINGLE CIRCUIT ELEMENTS SUCH AS CAPACITORS; RESISTORS; DIODES AND TRANSISTORS; PRINTED CIRCUIT BOARDS AND CIRCUIT CARD ASSEMBLIES; AND FILTERS AND NETWORKS.
Characteristics (Decoded)
| MRC | Requirements Statement | Clear Text Reply |
|---|---|---|
| CQSZ | INCLOSURE CONFIGURATION | DUAL-IN-LINE |
| AFGA | OPERATING TEMP RANGE | -55.0/+125.0 DEG CELSIUS |
| CTFT | CASE OUTLINE SOURCE AND DESIGNATOR | T0-116 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| CQZP | INPUT CIRCUIT PATTERN | HEX 1 INPUT |
| TTQY | TERMINAL TYPE AND QUANTITY | 14 PRINTED CIRCUIT |
| CSSL | DESIGN FUNCTION AND QUANTITY | 6 INVERTER, DIGITAL |
| CZEQ | TIME RATING PER CHACTERISTIC | 7.50 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 7.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |
| CZEN | VOLTAGE RATING AND TYPE PER CHARACTERISTIC | -1.5 VOLTS MINIMUM POWER SOURCE AND 5.5 VOLTS MAXIMUM POWER SOURCE |
| AEHX | MAXIMUM POWER DISSIPATION RATING | 279.0 MILLIWATTS |
| ADAU | BODY HEIGHT | 0.140 INCHES MINIMUM AND 0.180 INCHES MAXIMUM |
| AFJQ | STORAGE TEMP RANGE | -65.0/+150.0 DEG CELSIUS |
| CBBL | FEATURES PROVIDED | HERMETICALLY SEALED AND MONOLITHIC AND POSITIVE OUTPUTS AND HIGH SPEED AND SCHOTTKY AND W/OPEN COLLECTOR |
| ADAT | BODY WIDTH | 0.220 INCHES MINIMUM AND 0.280 INCHES MAXIMUM |
| CQSJ | INCLOSURE MATERIAL | CERAMIC AND GLASS |
| CQWX | OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| CWSG | TERMINAL SURFACE TREATMENT | SOLDER |
| ADAQ | BODY LENGTH | 0.660 INCHES MINIMUM AND 0.785 INCHES MAXIMUM |