Part Number
Part Number:
NSN:
NIIN:
Item Name:
MICROCIRCUIT , DIGITAL
Definition:
A MICROCIRCUIT SPECIFICALLY DESIGNED TO GENERATE, MODIFY, OR PROCESS ELECTRICAL SIGNALS WHICH OPERATE WITH TWO DISTINCT OR BINARY STATES. THESE STATES ARE COMMONLY REFERRED TO AS ON AND OFF, TRUE AND FALSE, HIGH AND LOW, OR "1" AND "0".
CAGE Information
| Code | Company |
|---|---|
| 80249 | BAE SYSTEMS INFORMATION AND ELECTRON |
Federal Supply Class
Title
MICROCIRCUITS, ELECTRONIC
Inclusions:
INCLUDES INTEGRATED CIRCUIT DEVICES; INTEGRATED CIRCUIT MODULES, INTEGRATED ELECTRONIC DEVICES: HYBRID, MAGNETIC, MOLECULAR, OPTO-ELECTRONIC, AND THIN FILM.
Exclusions:
EXCLUDES SINGLE CIRCUIT ELEMENTS SUCH AS CAPACITORS; RESISTORS; DIODES AND TRANSISTORS; PRINTED CIRCUIT BOARDS AND CIRCUIT CARD ASSEMBLIES; AND FILTERS AND NETWORKS.
Characteristics (Decoded)
| MRC | Requirements Statement | Clear Text Reply |
|---|---|---|
| AFGA | OPERATING TEMP RANGE | -55.0/+125.0 DEG CELSIUS |
| AFGA | OPERATING TEMP RANGE | -55.0/+125.0 DEG CELSIUS |
| AEHX | MAXIMUM POWER DISSIPATION RATING | 220.0 MILLIWATTS |
| CBBL | FEATURES PROVIDED | MONOLITHIC AND POSITIVE OUTPUTS AND MEDIUM POWER AND EDGE TRIGGERED AND PRESETTABLE AND HERMETICALLY SEALED AND MEDIUM SPEED AND W/CLEAR |
| CZEN | VOLTAGE RATING AND TYPE PER CHARACTERISTIC | -1.5 VOLTS MINIMUM POWER SOURCE AND 5.5 VOLTS MAXIMUM POWER SOURCE |
| CQSZ | INCLOSURE CONFIGURATION | FLAT PACK |
| TTQY | TERMINAL TYPE AND QUANTITY | 14 FLAT LEADS |
| AFJQ | STORAGE TEMP RANGE | -65.0/+150.0 DEG CELSIUS |
| ADAT | BODY WIDTH | 0.200 INCHES MINIMUM AND 0.300 INCHES MAXIMUM |
| CSSL | DESIGN FUNCTION AND QUANTITY | 2 FLIP-FLOP, CLOCKED AND 2 FLIP-FLOP, D-TYPE |
| CQZP | INPUT CIRCUIT PATTERN | DUAL 4 INPUT |
| ADAU | BODY HEIGHT | 0.008 INCHES MINIMUM AND 0.100 INCHES MAXIMUM |
| CQSJ | INCLOSURE MATERIAL | CERAMIC AND GLASS |
| CQWX | OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| ADAQ | BODY LENGTH | 0.337 INCHES MINIMUM AND 0.350 INCHES MAXIMUM |
| CZEQ | TIME RATING PER CHACTERISTIC | 39.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 50.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |
| CTFT | CASE OUTLINE SOURCE AND DESIGNATOR | -0-004-AA JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| TEST | TEST DATA DOCUMENT | 80249-911252 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING) |
| CWSG | TERMINAL SURFACE TREATMENT | SOLDER |