Part Number
Part Number:
NSN:
NIIN:
Item Name:
MICROCIRCUIT , DIGITAL
Definition:
A MICROCIRCUIT SPECIFICALLY DESIGNED TO GENERATE, MODIFY, OR PROCESS ELECTRICAL SIGNALS WHICH OPERATE WITH TWO DISTINCT OR BINARY STATES. THESE STATES ARE COMMONLY REFERRED TO AS ON AND OFF, TRUE AND FALSE, HIGH AND LOW, OR "1" AND "0".
CAGE Information
| Code | Company |
|---|---|
| 18324 | PHILIPS SEMICONDUCTORS INC |
Federal Supply Class
Title
MICROCIRCUITS, ELECTRONIC
Inclusions:
INCLUDES INTEGRATED CIRCUIT DEVICES; INTEGRATED CIRCUIT MODULES, INTEGRATED ELECTRONIC DEVICES: HYBRID, MAGNETIC, MOLECULAR, OPTO-ELECTRONIC, AND THIN FILM.
Exclusions:
EXCLUDES SINGLE CIRCUIT ELEMENTS SUCH AS CAPACITORS; RESISTORS; DIODES AND TRANSISTORS; PRINTED CIRCUIT BOARDS AND CIRCUIT CARD ASSEMBLIES; AND FILTERS AND NETWORKS.
Characteristics (Decoded)
| MRC | Requirements Statement | Clear Text Reply |
|---|---|---|
| AFGA | OPERATING TEMP RANGE | -55.0/+125.0 DEG CELSIUS |
| AFGA | OPERATING TEMP RANGE | -55.0/+125.0 DEG CELSIUS |
| AFJQ | STORAGE TEMP RANGE | -65.0/+200.0 DEG CELSIUS |
| CQZP | INPUT CIRCUIT PATTERN | 9 INPUT |
| CQWX | OUTPUT LOGIC FORM | EMITTER-COUPLED LOGIC |
| CZEQ | TIME RATING PER CHACTERISTIC | 50.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 50.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |
| CQSZ | INCLOSURE CONFIGURATION | FLAT PACK |
| TTQY | TERMINAL TYPE AND QUANTITY | 14 FLAT LEADS |
| ADAT | BODY WIDTH | 0.200 INCHES MINIMUM AND 0.300 INCHES MAXIMUM |
| CZEN | VOLTAGE RATING AND TYPE PER CHARACTERISTIC | 5.5 VOLTS MAXIMUM POWER SOURCE |
| CBBL | FEATURES PROVIDED | SYNCHRONOUS AND POSITIVE OUTPUTS AND MONOLITHIC AND EDGE TRIGGERED AND HIGH SPEED AND ASYNCHRONOUS AND HERMETICALLY SEALED AND RESETTABLE |
| ADAU | BODY HEIGHT | 0.008 INCHES MINIMUM AND 0.100 INCHES MAXIMUM |
| CQSJ | INCLOSURE MATERIAL | CERAMIC AND GLASS |
| ADAQ | BODY LENGTH | 0.330 INCHES MINIMUM AND 0.350 INCHES MAXIMUM |
| AEHX | MAXIMUM POWER DISSIPATION RATING | 132.0 MILLIWATTS |
| CSSL | DESIGN FUNCTION AND QUANTITY | 1 FLIP-FLOP, J-K, CLOCKED |
| CTFT | CASE OUTLINE SOURCE AND DESIGNATOR | -0-004-AA JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| CWSG | TERMINAL SURFACE TREATMENT | SOLDER |