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Part Number

Part Number:
NSN:
NIIN:
Item Name:
MICROCIRCUIT , DIGITAL

Definition:

A MICROCIRCUIT SPECIFICALLY DESIGNED TO GENERATE, MODIFY, OR PROCESS ELECTRICAL SIGNALS WHICH OPERATE WITH TWO DISTINCT OR BINARY STATES. THESE STATES ARE COMMONLY REFERRED TO AS ON AND OFF, TRUE AND FALSE, HIGH AND LOW, OR "1" AND "0".

CAGE Information

Code Company
27014 NATIONAL SEMICONDUCTOR CORPORATION

Characteristics (Decoded)

MRC Requirements Statement Clear Text Reply
CBBL FEATURES PROVIDED W/ENABLE AND W/CLEAR AND POSITIVE OUTPUTS AND MONOLITHIC AND HERMETICALLY SEALED AND LOW POWER
AFGA OPERATING TEMP RANGE -55.0/+125.0 DEG CELSIUS
CSSL DESIGN FUNCTION AND QUANTITY 2 FLIP-FLOP, J-K, MASTER SLAVE
AEHX MAXIMUM POWER DISSIPATION RATING 90.0 MILLIWATTS
CQSZ INCLOSURE CONFIGURATION FLAT PACK
TTQY TERMINAL TYPE AND QUANTITY 14 FLAT LEADS
AFJQ STORAGE TEMP RANGE -65.0/+150.0 DEG CELSIUS
CZEN VOLTAGE RATING AND TYPE PER CHARACTERISTIC 5.5 VOLTS MAXIMUM POWER SOURCE
ADAU BODY HEIGHT 0.045 INCHES MINIMUM AND 0.085 INCHES MAXIMUM
ADAT BODY WIDTH 0.235 INCHES MINIMUM AND 0.260 INCHES MAXIMUM
CQZP INPUT CIRCUIT PATTERN DUAL 4 INPUT
CQSJ INCLOSURE MATERIAL CERAMIC AND GLASS
CQWX OUTPUT LOGIC FORM TRANSISTOR-TRANSISTOR LOGIC
ADAQ BODY LENGTH 0.390 INCHES MAXIMUM
CZEQ TIME RATING PER CHACTERISTIC 15.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 15.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT
TEST TEST DATA DOCUMENT 88818-A574A015 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING)
CWSG TERMINAL SURFACE TREATMENT SOLDER

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