Part Number
Part Number:
NSN:
NIIN:
Item Name:
MICROCIRCUIT , DIGITAL
Definition:
A MICROCIRCUIT SPECIFICALLY DESIGNED TO GENERATE, MODIFY, OR PROCESS ELECTRICAL SIGNALS WHICH OPERATE WITH TWO DISTINCT OR BINARY STATES. THESE STATES ARE COMMONLY REFERRED TO AS ON AND OFF, TRUE AND FALSE, HIGH AND LOW, OR "1" AND "0".
CAGE Information
Code | Company |
---|---|
01295 | TEXAS INSTRUMENTS INCORPORATED DBA T |
Federal Supply Class
Title
MICROCIRCUITS, ELECTRONIC
Inclusions:
INCLUDES INTEGRATED CIRCUIT DEVICES; INTEGRATED CIRCUIT MODULES, INTEGRATED ELECTRONIC DEVICES: HYBRID, MAGNETIC, MOLECULAR, OPTO-ELECTRONIC, AND THIN FILM.
Exclusions:
EXCLUDES SINGLE CIRCUIT ELEMENTS SUCH AS CAPACITORS; RESISTORS; DIODES AND TRANSISTORS; PRINTED CIRCUIT BOARDS AND CIRCUIT CARD ASSEMBLIES; AND FILTERS AND NETWORKS.
Characteristics (Decoded)
MRC | Requirements Statement | Clear Text Reply |
---|---|---|
AFGA | OPERATING TEMP RANGE | -55.0/+125.0 DEG CELSIUS |
AFGA | OPERATING TEMP RANGE | -55.0/+125.0 DEG CELSIUS |
PRMT | PRECIOUS MATERIAL | GOLD |
ADAU | BODY HEIGHT | 0.035 INCHES MINIMUM AND 0.050 INCHES MAXIMUM |
ADAQ | BODY LENGTH | 0.250 INCHES MINIMUM AND 0.260 INCHES MAXIMUM |
CQSJ | INCLOSURE MATERIAL | GLASS AND METAL |
CSSL | DESIGN FUNCTION AND QUANTITY | 4 GATE, NOR |
CQSZ | INCLOSURE CONFIGURATION | FLAT PACK |
FEAT | SPECIAL FEATURES | FORMED LEADS; INSULATOR FURNISHED; MECH-PAKETTE FURNISHED |
AFJQ | STORAGE TEMP RANGE | -65.0/+150.0 DEG CELSIUS |
AEHX | MAXIMUM POWER DISSIPATION RATING | 240.0 MILLIWATTS |
CQWX | OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
CQZP | INPUT CIRCUIT PATTERN | QUAD 2 INPUT |
CBBL | FEATURES PROVIDED | MEDIUM SPEED AND HERMETICALLY SEALED AND MONOLITHIC AND POSITIVE OUTPUTS AND MEDIUM POWER AND W/TOTEM POLE OUTPUT |
PMLC | PRECIOUS MATERIAL AND LOCATION | TERMINALS GOLD AND BODY GOLD |
ADAT | BODY WIDTH | 0.140 INCHES MINIMUM AND 0.150 INCHES MAXIMUM |
CZEQ | TIME RATING PER CHACTERISTIC | 22.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 15.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |
CTFT | CASE OUTLINE SOURCE AND DESIGNATOR | T0-84 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |