Part Number
Part Number:
NSN:
NIIN:
Item Name:
MICROCIRCUIT , DIGITAL
Definition:
A MICROCIRCUIT SPECIFICALLY DESIGNED TO GENERATE, MODIFY, OR PROCESS ELECTRICAL SIGNALS WHICH OPERATE WITH TWO DISTINCT OR BINARY STATES. THESE STATES ARE COMMONLY REFERRED TO AS ON AND OFF, TRUE AND FALSE, HIGH AND LOW, OR "1" AND "0".
CAGE Information
Code | Company |
---|---|
27014 | NATIONAL SEMICONDUCTOR CORPORATION |
Federal Supply Class
Title
MICROCIRCUITS, ELECTRONIC
Inclusions:
INCLUDES INTEGRATED CIRCUIT DEVICES; INTEGRATED CIRCUIT MODULES, INTEGRATED ELECTRONIC DEVICES: HYBRID, MAGNETIC, MOLECULAR, OPTO-ELECTRONIC, AND THIN FILM.
Exclusions:
EXCLUDES SINGLE CIRCUIT ELEMENTS SUCH AS CAPACITORS; RESISTORS; DIODES AND TRANSISTORS; PRINTED CIRCUIT BOARDS AND CIRCUIT CARD ASSEMBLIES; AND FILTERS AND NETWORKS.
Characteristics (Decoded)
MRC | Requirements Statement | Clear Text Reply |
---|---|---|
AFGA | OPERATING TEMP RANGE | -55.0/+125.0 DEG CELSIUS |
AFGA | OPERATING TEMP RANGE | -55.0/+125.0 DEG CELSIUS |
PRMT | PRECIOUS MATERIAL | GOLD |
ADAU | BODY HEIGHT | 0.035 INCHES MINIMUM AND 0.050 INCHES MAXIMUM |
CBBL | FEATURES PROVIDED | LOW POWER AND MONOLITHIC AND HERMETICALLY SEALED AND POSITIVE OUTPUTS AND W/TOTEM POLE OUTPUT |
ADAQ | BODY LENGTH | 0.250 INCHES MINIMUM AND 0.260 INCHES MAXIMUM |
CQSJ | INCLOSURE MATERIAL | GLASS AND METAL |
CWSG | TERMINAL SURFACE TREATMENT | GOLD |
AEHX | MAXIMUM POWER DISSIPATION RATING | 12.0 MILLIWATTS |
CQSZ | INCLOSURE CONFIGURATION | FLAT PACK |
TTQY | TERMINAL TYPE AND QUANTITY | 14 FLAT LEADS |
AFJQ | STORAGE TEMP RANGE | -65.0/+150.0 DEG CELSIUS |
CQZP | INPUT CIRCUIT PATTERN | TRIPLE 3 INPUT |
CZEN | VOLTAGE RATING AND TYPE PER CHARACTERISTIC | 5.5 VOLTS MAXIMUM POWER SOURCE |
CSSL | DESIGN FUNCTION AND QUANTITY | 3 GATE, NAND |
TEST | TEST DATA DOCUMENT | 06481-970078 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING) |
CQWX | OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
CZEQ | TIME RATING PER CHACTERISTIC | 60.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 60.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |
PMLC | PRECIOUS MATERIAL AND LOCATION | TERMINALS GOLD AND BODY GOLD |
ADAT | BODY WIDTH | 0.140 INCHES MINIMUM AND 0.150 INCHES MAXIMUM |
CTFT | CASE OUTLINE SOURCE AND DESIGNATOR | T0-84 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |