Part Number
Part Number:
NSN:
NIIN:
Item Name:
MICROCIRCUIT , DIGITAL
Definition:
A MICROCIRCUIT SPECIFICALLY DESIGNED TO GENERATE, MODIFY, OR PROCESS ELECTRICAL SIGNALS WHICH OPERATE WITH TWO DISTINCT OR BINARY STATES. THESE STATES ARE COMMONLY REFERRED TO AS ON AND OFF, TRUE AND FALSE, HIGH AND LOW, OR "1" AND "0".
CAGE Information
| Code | Company |
|---|---|
| 01295 | TEXAS INSTRUMENTS INCORPORATED DBA T |
Federal Supply Class
Title
MICROCIRCUITS, ELECTRONIC
Inclusions:
INCLUDES INTEGRATED CIRCUIT DEVICES; INTEGRATED CIRCUIT MODULES, INTEGRATED ELECTRONIC DEVICES: HYBRID, MAGNETIC, MOLECULAR, OPTO-ELECTRONIC, AND THIN FILM.
Exclusions:
EXCLUDES SINGLE CIRCUIT ELEMENTS SUCH AS CAPACITORS; RESISTORS; DIODES AND TRANSISTORS; PRINTED CIRCUIT BOARDS AND CIRCUIT CARD ASSEMBLIES; AND FILTERS AND NETWORKS.
Characteristics (Decoded)
| MRC | Requirements Statement | Clear Text Reply |
|---|---|---|
| PMLC | PRECIOUS MATERIAL AND LOCATION | TERMINAL SURFACE GOLD |
| AFGA | OPERATING TEMP RANGE | -55.0/+125.0 DEG CELSIUS |
| TEST | TEST DATA DOCUMENT | 14715-8001800026 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING) |
| PRMT | PRECIOUS MATERIAL | GOLD |
| CWSG | TERMINAL SURFACE TREATMENT | GOLD |
| ADAT | BODY WIDTH | 0.120 INCHES MINIMUM AND 0.150 INCHES MAXIMUM |
| AEHX | MAXIMUM POWER DISSIPATION RATING | 40.0 MILLIWATTS |
| CZEN | VOLTAGE RATING AND TYPE PER CHARACTERISTIC | -1.5 VOLTS MINIMUM POWER SOURCE AND 5.5 VOLTS MAXIMUM POWER SOURCE |
| CQSZ | INCLOSURE CONFIGURATION | FLAT PACK |
| TTQY | TERMINAL TYPE AND QUANTITY | 14 FLAT LEADS |
| AFJQ | STORAGE TEMP RANGE | -65.0/+150.0 DEG CELSIUS |
| CBBL | FEATURES PROVIDED | MONOLITHIC AND HERMETICALLY SEALED AND POSITIVE OUTPUTS AND MEDIUM SPEED AND W/OPEN COLLECTOR |
| ADAU | BODY HEIGHT | 0.030 INCHES MINIMUM AND 0.070 INCHES MAXIMUM |
| ADAQ | BODY LENGTH | 0.240 INCHES MINIMUM AND 0.260 INCHES MAXIMUM |
| CQSJ | INCLOSURE MATERIAL | CERAMIC AND GLASS |
| CQWX | OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| CQZP | INPUT CIRCUIT PATTERN | QUAD 2 INPUT |
| CSSL | DESIGN FUNCTION AND QUANTITY | 4 GATE, NAND |
| CZEQ | TIME RATING PER CHACTERISTIC | 45.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 15.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |
| CTFT | CASE OUTLINE SOURCE AND DESIGNATOR | T0-84 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |